Re: Dropped frames in video capture process
Vassili Leonov (vleo@pcisys.net)
Fri, 6 Nov 1998 01:19:27 -0700
>To: vleo@pcisys.net (Vassili Leonov)
>Date: Fri, 6 Nov 1998 07:21:24 +0100 (MET)
>From: R.E.Wolff@BitWizard.nl (Rogier Wolff)
>
>Page 27 of the datasheet.
>
>13.6 Video Stride, Status and Frame Grab Register
>
>This register contains parameters for display addressing (bytes 2-3),
>status of VFIFO (byte 1) and frame grab control (byte 0). display.
>Address Offset: 0x014 Bit
>[....]
> 8 RC all VidOvf - Video FIFO Overflow flag. This bit is asserted by
>the Video FIFO server when an overflow of the Video FIFO occurs. This
>bit is cleared when the host tries to write '1' to it. In case of
>concurrent accesses to this bit, it remains '1'.
> '1' - a VFIFO overflow occurred.
> '0' - no overflow (default value).
>
>Case closed.
If you look on page 6, there is 067 block diagram. At the top of
it there is Video FIFO. That's the one that is referred on page 27 of
the datasheet.
At the bottom of the diagram there is Code FIFO. That one is used to
transfer JPEG code from 060 into system memory. I'm not using Video
FIFO in the compression mode at all.
So, I would not be so quick closing cases...
As I said, I can wire the 060 DATAERR signal to GIRQ1 and have that
status there. On top of that, we were talking about the FIFO on
060, not 067 anyway.
Vassili.
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