Re: [PATCH 2/4] spi: spi-fsl-dspi: Use non-coherent memory for DMA

From: James Clark
Date: Thu Jun 12 2025 - 10:41:06 EST




On 12/06/2025 3:31 pm, Vladimir Oltean wrote:
On Thu, Jun 12, 2025 at 03:28:37PM +0100, James Clark wrote:


On 12/06/2025 3:23 pm, Vladimir Oltean wrote:
On Thu, Jun 12, 2025 at 03:14:32PM +0100, James Clark wrote:
That's why I don't like the DMA mode in DSPI, it's still CPU-bound,
because the DMA buffers are very small (you can only provide one TX FIFO
worth of data per DMA transfer, rather than the whole buffer).

Is that right? The FIFO size isn't used in any of the DMA codepaths, it
looks like the whole DMA buffer is filled before initiating the transfer.
And we increase the buffer to 4k in this patchset to fully use the existing
allocation.

Uhm, yeah, no?

dspi_dma_xfer():

while (dspi->len) {
dspi->words_in_flight = dspi->len / dspi->oper_word_size;
if (dspi->words_in_flight > dspi->devtype_data->fifo_size)
dspi->words_in_flight = dspi->devtype_data->fifo_size;
dspi_next_xfer_dma_submit();
}

Right but that's before the change in this patchset to use the whole page
that was allocated, hence the next bit:

And we increase the buffer to 4k in this patchset to fully use the
existing allocation.

We were allocating for the size of the FIFO (multiplied by two to hold the
control words), but dma_alloc_coherent() will be backed by a whole page
anyway, even if you only ask for a few bytes.

After changing that to make use of the full allocation the FIFO length is no
longer involved.

Ok, I haven't walked through patch 3 yet, I didn't realize it would be
changing that. I will want to test it on LS1028A.

Yeah testing it somewhere else would be good. Maybe there is some limitation there about the max size of the DMA transfer, but I didn't see it.

I realise the tense in my original message may have been a bit confusing. I was mixing up the existing code and proposed changes...