Re: [PATCH] clk: tegra: initialise parent of uart clocks

From: Laxman Dewangan
Date: Tue Feb 12 2013 - 10:23:14 EST

On Wednesday 06 February 2013 11:13 PM, Stephen Warren wrote:
On 02/06/2013 03:47 AM, Laxman Dewangan wrote:
Initialise the parent of UARTs to PLLP

and disabling clock by default.
Hmm. Only the clocks initialized by the new entries you added are marked
disabled (or rather, not actively enabled; if they're enabled already,
they won't be disabled). We should treat all UARTs equally. Historically
we've needed to enable the serial clocks forcibly since the regular
serial driver didn't call clk_get() or clk_prepare_enable() on any
clocks, but I notice that it does now, since sometime in kernel 3.8. As
such, I think you can modify all the UART entries in these tables to
have the enable/state field set to false (0). Can you try that and check
that it works for the serial console ports? Thanks.

Yes, this work even if I make state to 0 (disabled) in clock init table. The of_serial driver call the clk_prepare_enable() if property "clock_frequency" is there in dt node and in our dts file, we have already this property.

I sent V2 patch.

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