Re: [PATCH] clk: tegra: initialise parent of uart clocks

From: Laxman Dewangan
Date: Tue Feb 12 2013 - 10:20:16 EST

On Tuesday 12 February 2013 08:47 PM, Laxman Dewangan wrote:
Initialise the parent of UARTs to PLLP and disabling clock by

Signed-off-by: Laxman Dewangan <ldewangan@xxxxxxxxxx>

Please ignore this, I just sent the other patch as V2 to have more appropriate version. Please review the Patch V2.
Sorry for spam/inconvenience.

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