Re: [PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset

From: Andi Kleen
Date: Tue Feb 12 2013 - 10:14:32 EST

On Tue, Feb 12, 2013 at 09:43:46AM +0100, Ingo Molnar wrote:
> Was this stress-tested on all affected main CPU types, or only
> on Haswell?

I tested it on Haswell and Ivy Bridge. I can also try
Westmere and a Saltwell(Atom), but for the majority of other family 6
systems I'll need to rely on the community.

White listing is somewhat difficult because it affects the architectural
mode too.

I don't really expect problems from this change, we should probably
have always done it like this.


ak@xxxxxxxxxxxxxxx -- Speaking for myself only.
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