Re: [PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handlerafter the counter registers are reset

From: Ingo Molnar
Date: Tue Feb 12 2013 - 03:43:56 EST

* Andi Kleen <andi@xxxxxxxxxxxxxx> wrote:

> From: Andi Kleen <ak@xxxxxxxxxxxxxxx>
> This avoids some problems with spurious PMIs on Haswell.
> Haswell seems to behave more like P4 in this regard. Do
> the same thing as the P4 perf handler by unmasking
> the NMI only at the end. Shouldn't make any difference
> for earlier non P4 cores.

Was this stress-tested on all affected main CPU types, or only
on Haswell?


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