Andrey Savochkin wrote:
>
> Hello,
>
> On Fri, May 19, 2000 at 04:38:20PM -0700, Dragan Stancevic wrote:
> > On Fri, May 19, 2000, Kamlesh Bans <kbans@corsair.com> wrote:
> > ;
> > ; The "res2" patch Andrey sent me (adding #define USE_IO to the 1.20.2.5
> > ; driver) works! Hooray!
> >
> >
> > Good spoting Andrey, that explains eeprom checksum :^)
>
> 8-()
>
> It doesn't explain it for me!
> The question is not in the delay. Udelay(100) didn't help.
> It's USE_IO that fixed things for Kamlesh.
It sounds like MMIO flushing might be a problem.
> Well, I've heard from other l-k discussions that memory mapping PCI IO isn't
> very easy. Different write operations may be reordered or coalesced.
> I would appreciate if someone with PCI knowledge elaborates it for me and
> gives a hint how to do several writes to a single address with guarantee that
> they are committed as they are.
I plan to put the following wisdom into pci.txt. As told to me from
Alan, who claims that Gerard Roudier is the real expert. Gerard in
turns claims nothing more than actually reading the PCI spec. :)
1) PCI will delay writes, group writes together but it will not re-order
them or let reads pass writes. [thus, a readl() will cause a PCI flush
of all delayed writes]
2) [What happens when two CPUs two to MMIO spaces at the "same time"?]
Both writes will occur. The ordering will be the CPU ordering. It may
turn them both into a single burst write if they are adjacent and the
ordering is lower->higher
-- Jeff Garzik | Liberty is always dangerous, but Building 1024 | it is the safest thing we have. MandrakeSoft, Inc. | -- Harry Emerson Fosdick- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.rutgers.edu Please read the FAQ at http://www.tux.org/lkml/
This archive was generated by hypermail 2b29 : Tue May 23 2000 - 21:00:19 EST