Re: Nested interrupt confusion
Richard B. Johnson (root@chaos.analogic.com)
Thu, 10 Jun 1999 21:46:08 -0400 (EDT)
On Thu, 10 Jun 1999, B. James Phillippe wrote:
>
> Sorry, this is the right answer to the wrong question; I'm aware of how the
> situation works for that same IRQ, but that's not what I'm asking about.
> I'm asking about nested dissimilar interrupts, not re-entered interrupts.
> Like this:
>
> Slow Interrupt A ISR entered (ie. no SA_INTERRUPT)
> Interrupt A already disabled in interrupt controller
> Other interrupts still enabled in controller and microprocessor
> ----Interrupt B for unrelated device is asserted, ISR B entered
> Interrupt B disabled in interrupt controller
> Other interrupts still enabled in IC and CPU
> ----Interrupt B finishes
> Stack unwound, interrupt A ISR resumes
> Interrupt A ISR finishes
>
> Is this possible? It appears to be possible on x86, but not on Alpha (ie.
> on Alpha in arch/alpha/kernel/irq.c, interrupt reporting is disabled in the
> microprocessor prior to ISR execution). In the x86 case, if it is
> supported (as it appears to be), how deep can this happen? Is it only
> limited by available number of interrupts that can possibly fire before
> they are all masked off?
Someone with Alpha experience will have to answer the Alpha question.
With the x86, nested interrupts (at other than the current level) is
supported.
Therefore, the kernel, in the interrupt context, can be interrupted.
The amount of nesting is controlled only by the available interrupt
levels, i.e., 15 (one is the cascade). ISRs generally don't use
a lot of stack because they have to get/put data from something persistent
so there should be enough stack to handle whatever you have.
The last time I checked, the kernel stack is limited to only one page
(4096 bytes in x86, 8192 on Alpha), you could check the sources to see
if it is now greater.
Cheers,
Dick Johnson
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