I had a cunning thought a couple of weeks back which people seem to think
will work, but no-one's done yet :-)
The problem is that if the SWP instruction (atomically read-and-write)
hits in the cache, it will not go through to main memory, unlike earlier
ARM processors. Obviously, disabling the cache is going to take a big
performance hit (particularly for those of us with 33MHz busses, argh).
My proposed solution is to define ARM spinlocks to be a pointer to an
address which is in a uncached area of RAM. This should keep everything
consistent at the cost of an additional memory access to take and release
a lock. This shouldn't be too much of a problem since the pointer can
live in cache if it is frequently accessed.
Of course, the point is moot until anyone has any SMP-capable hardware
to play with. I can't solder. I believe Causality are going to produce
a card with several ARMs on it, but I've not heard anything recently.
-- Matthew Wilcox <willy@bofh.ai> "Windows and MacOS are products, contrived by engineers in the service of specific companies. Unix, by contrast, is not so much a product as it is a painstakingly compiled oral history of the hacker subculture." - N Stephenson- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.rutgers.edu Please read the FAQ at http://www.tux.org/lkml/