> On Tue, 11 May 1999, Martin Mares wrote:
>
> > Hello!
> >
> > > Finally I'm able to come back to the discussion of this problem. Now it's
> > > showing up on a Dell PowerEdge 1300 (a pretty new system, I must say ...),
> > > and the information for the "failing" system comes from this PowerEdge.
> > >
> > > Just to refresh your minds, the problem is that a PLX9080-based PCI board
> > > has an I/O address assigned to it when it actually requested a 32-bit
> > > memory address (more specifically, the PCI Base Address 2).
> >
> > I'm pretty sure it's a hardware problem -- the lowest bit of the base
> > address register (which says whether it's a memory region or an I/O
> > region) must be hard-wired and thus not changeable by the software.
> > [PCI specs, section 6.2.5.1]
>
> Yes, I know that, and PLX has told me that these bits are hardwired once
> the BIOS has programmed it.
What BIOS ?
The PCI initialization software (or PCI BIOS) uses generic algorithms to
assign ressources. The bits that define the attributes of the base address
registers must be hardwired prior to the PCI BIOS assigning ressources.
The weird thing is that the PCI BIOS seems to have assigned an address
that looks like a MMIO address to an address register that seems flagged
for normal IO.
Perhaps, the PCI BIOS is just assuming that only address register #0 can
be IO, or the offending bit was ok at the moment the PCI BIOS assigned the
resource.
> I have a question though: if it is a hardware problem, then why does the
> card correctly allocates the base address 2 as MEMORY under Windows NT and
> DOS ?? It's at least intriguing that this allocation _only_ fails on Linux
> ...
If you load some driver or anything that knows about the device, it may
apply some work-around in your back. So you should just boot DOS without
running anything else and then read the config space of the device using
the debug command, as follows:
- Write the enable_bit/#bus/#device/#function/#register DWORD value (1) to
address 0xCF8.
- Read the result (DWORD) from address 0xCFC
enable_bit = bit 31
bus number = bit 16..23
device number = bit 11..15
function number = bit 8..10
register = 0x10 for base address #0, 0x14 for base address # 1
and so on ...
(bit 0,1=0)
(1) For bus 2, device 9, function 0, base address register 1 (0x14),
the value to write to 0xCF8 should be something like:
-> 1000 0000 0000 0010 0010 0100 0001 0100
-> 0x80022414 [modulo some calculation errors]
Gérard.
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