>> On the other hand - WHY one loses portability doing IO memory access
>> on different architectures? Sure enough that PCI memory would be
>> present on any architecture that has that PCI plugged in, and
>> registers would be the same (though ordering might differ, and that
>> is the responsibility of writel() etc. to handle it.
Alan> Does the bus reverse the bytes in the long words, does it do PCI
Alan> posting, how is I/O space mapped - memory, I/O instructions, are
Alan> different size or endian mappings present at different offsets.
Alan> Then you can add write posting, cache coherency and the like.
Ok, then what IS the proper way of accessing the PCI mem space? There
are some drivers (drivers/net/dgrs.c for instance) that just do:
ulong *ptr = ioremap(physaddr, 256);
ptr[3] = something;
Others use writel()/readl(), some define their own macros. Is there a
One True Way?
Does one need to worry about caching and cache flushing in case of PCI
mem space? Is that architecture dependent?
--J.
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