Re: [patch] cycle-counter synchronization on SMP, 2.2.0-final

Mark-Andre Hopf (hopf@informatik.uni-rostock.de)
Fri, 22 Jan 1999 20:47:07 +0100 (MET)


MOLNAR Ingo wrote:

> On Fri, 22 Jan 1999, Mark-Andre Hopf wrote:
>
> > My first assumption, my large difference in the TSC registers was wrong,
> > so I guess this bug should be visible on other Intel SMP systems too,
> > maybe even UP systems. [...]
>
> (btw. i have noticed timestamp-counter anomalies on overclocked CPUs.
> Everything was OK, but the timestamp-counter got corrupted sometimes)
>
> if it's asynchron cycle-counters on SMP, then could you try the attached
> patch? I didnt want to deal with this because most systems have a synchron
> cycle counter, but it seems to be more widespread than suspected ...
>
> with the patch installed my box synchronizes all 4 CPUs on bootup:
>
> [... bootlog ...]
> checking TSC synchronization across CPUs: passed.
> [...]
>
> what does it output on your system?

It says:

checking TSC synchronization across CPUs:
BIOS BUG: CPU#1 inproperly initialized, has 26 usecs TSC scew! FIXED.
BIOS BUG: CPU#1 inproperly initialized, has 26 usecs TSC scew! FIXED.

and it's a wonderful patch! `gettimeofday' is working correct with it.
I can't see no reason why it prints the second line two times, the CPU
number should've been different, right?, but it's okay here.

I bet my machine is not overclocked, IBM sells it like this. It's an IBM PC
Server 325.

Hmm, is this a reason for a specific guy, we all love so much, to "wear a
brown paper bag over his head for a month"? :)

Thanks a lot,
Mark

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