Re: pre-2.1.132-2..

Jamie Lokier (lkd@tantalophile.demon.co.uk)
Sun, 20 Dec 1998 02:22:28 +0000

On Fri, Dec 18, 1998 at 04:46:13PM +0100, MOLNAR Ingo wrote:
> > Note that we probably don't have a cache-line per CPU anyway, because
> > there is nothing to force proper alignment of the irq_desc[] array.
>
> instead of living with the imperfect alignment, in 2.3 we might want to
> create an 'smp_aligned' section (just like initdata), which is checked
> during kernel build (after linkage) against alignment violations. (it
> would be word aligned in the UP compilation case)

Or use macros to define per-cpu data, which is replicated to a sequence
of fixed address, separated by some power of two (e.g. 4k). That uses
less space for padding, lowers cache pressure, and it will work whatever
the cache line size. And you don't have to check anything.

You can't use the efficient x86 addressing modes with this (for
multiples of 1, 2, 4 or 8), but you can't do that anyway for structures
aligned to a multiple of 16 or 32 bytes.

-- Jamie

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