>
>
>On Fri, 18 Dec 1998, MOLNAR Ingo wrote:
>>
>> NO! :) On SMP, with shared data structures, we want to have 1 structure
>> per cacheline, otherwise we'd just play cacheline ping-pong for no good
>> reason.
>
>Note that we probably don't have a cache-line per CPU anyway, because
>there is nothing to force proper alignment of the irq_desc[] array.
Infact, I just noticed and fixed it myself once I understood the SMP cache
line issue....
>> (the padding is wrong in both cases btw, unless i cant count (damn, where
>> was that calculator). We need unused[5])
>
>Strange counting.
I guess he said we need_ed_ unused[5]. Now we need [4].
>Anyway, currently the alignment is wrong, and the size is wrong. The size
>is wrong because the original structure looked different, and one of the
>changes must have messed that up. Oh, well.
;)
>I suspect that we could actually get rid of the padding altogether, and
>align it to a 16-byte boundary. Then it wouldn't be cache-line aligned,
Intel specs say that it must have the first 5 bits zeroed to be cache
aligned.
>but it _would_ be half-cache-line aligned and thus at least partly
>minimize the overhead.
Since we just waste 64*4 byte in the struct, we could waste 16 more bytes
to be completly aligned I think...
Andrea Arcangeli
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