Re: 4MB pages and framebuffer access, x11perf results, 2.1.125

MOLNAR Ingo (mingo@chiara.csoma.elte.hu)
Thu, 29 Oct 1998 18:56:23 +0100 (CET)


On Thu, 29 Oct 1998, Alan Cox wrote:

> There are quite a few applications of 8Gig of RAM beyond database caches.
> Has anyone (intel or otherwise) actually quantified the impact of 3 level
> page tables. The xeon document extensions don't seem to provide much
> information on this, or on the impact of using 2 or 3 layer tables according
> to process type

well, first, page table entries are twice that big, 64-bit instead of
32-bit. This doubles the size of page tables, doubles the footprint in the
cache. The second effect is that TLB misses probably are twice as
expensive, this slows down context switches too. fork() and exec() cost
should almost double accordingly. Plus, who knows what kinds of
unannounced erratas there are waiting for us ...

[also, the update and access of page table entries is i think still not
completely locked, as while we can do atomic updates on 32-bit entries,
it's not all that easy (and cheap) to get it done on 64-bit entries.]

-- mingo

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