Re: 4MB pages and framebuffer access, x11perf results, 2.1.125

Linus Torvalds (torvalds@transmeta.com)
Thu, 29 Oct 1998 10:04:11 -0800 (PST)


On Thu, 29 Oct 1998, Alan Cox wrote:
>
> There are quite a few applications of 8Gig of RAM beyond database caches.
> Has anyone (intel or otherwise) actually quantified the impact of 3 level
> page tables.

It makes a TLB miss about 50% slower and our VM handling much bigger (MUCH
bigger, considering how bad gcc is at handling anything that is larger
than a machine word).

There shouldn't be much other impact.

However, it still doesn't make the kernel able to handle all the RAM due
to the kernel mapping issue. We could possibly take anonymous pages from
there (but "ptrace()" wouldn't be able to see them, for example), but the
only obvious use for them really is RAM-disk like caching.

This really is not something I'm willing to crap up the Linux MM for.
64-bit architectures are here to stay, I refuse to add the MicroSoft kind
of crap that will stay around forever to my kernel just to handle things
that most people don't care that much about.

Note that the _new_ 36-bit extemsions (new as of Xeon and later
PentiumII's) expressly allow 36-bit access with a two-level page table.
The high blocks can only be accessed with a 4MB page, but considering that
we'd probably be able to use it only as a RAM-disk anyway, that's fine.

And btw, this is what NT is doing too. Even the MS designers yelped at
adding crap to their heap of refuse.

Linus

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