> Hello,
>
> > I am currently writing some code that is intended to support the
> > SYMBIOS 53C896 64 bit PCI SCSI controller.
> > As you know, 64 bit PCI devices may use 64 bit address registers.
> >
> > This PCI device is using the following ones:
> >
> > - Register 10-13h
> > Base Address Register Zero (I/O)
> > - Register 14-1Bh (64 bit)
> > Base Address Register One (MMIO)
> > - Register 1C-23h (64 bit)
> > Base Address Register Two (RAM 8k)
> >
> > If I assume (probably wrongly) that each architecture provides a set
> > of PCI BIOS compatible services, I can easily deal with address registers
>
> All architectures do support PCI BIOS compatible services, but you
> should not use them for reading of base addresses and IRQs since some
> architectures (e.g. UltraSPARC) remap them to locations not representable
> in the configuration registers (32-bit IRQ numbers and 64-bit base
> addresses).
Ok.
> > for the SYM53C896 (even on a 32 bit PCI BUS where such a chip may be
> > installed). But, AFAIK, linux-2.1 uses a new interface for PCI
> > configuration accesses that is neither PCI BIOS - like, nor compatible.
> >
> > I have some questions:
> >
> > 1 - Which is the right kernel interface to use for 64 bit PCI and how must
> > I use it for accessing the address registers of this PCI device.
>
> Just use the base addresses stored in struct pci_dev and never read
> the real address registers yourself.
>
> > 2 - How much ready for 64 bit bit devices is Linux ?
>
> I've never tested the Linux PCI code with real 64 bit devices, but it should
> be able to handle them correctly:
>
> - On 32-bit machines it's just able to read the 64 bit address and
> throws out the device if it's been configured by the BIOS to use
> addresses outside the 32 bit range the machine can handle.
Why such a software limitation?
It is not necessary for a driver to be able to address all the device
PCI bus address windows in order to work. For example, using a ia32 in 16
bit mode, we could do the following:
1 - Use normal IOs for IO register accesses (if in 16 bit range).
2 - Provide Memory Bus Addresses for DMA (scatter entries) in memory and
let the device get them by itself from the PCI BUS.
(BTW, the 53C8XX chip are also able to load their on-board RAM by
themselves using a mini-script in memory that performs the move
from host memory to the chip RAM)
The same scheme can be used for a 64 bit device on 64 bit PCI bus driven
from a 32 bit CPU and AFAIK, the Pentia II allows 36 bit addressing for
host memory. So, 64 bit PCI could be used on ia32 in order to DMA into the
whole 36 bit address range.
> - On 64-bit machines it fetches the whole address and the corresponding
> pci_dev struct fields are large enough to hold it. Anyway, I'm not sure
> all architectures are able to assign addresses to 64-bit devices
> correctly.
Looking into the code, it seems that some arch are not quite ok for 64 bit
PCI.
32 bit PCI on 64 bit systems requires bounce buffers for DMAing more than
4 GB. IMO, 64 bit systems that allows more than 4 GB and that donnot
provide 64 bit PCI are not quite serious anyway.
Am I wrong?
Gerard.
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