They are wrong, or at least misleading (in many cases, not only this one)
> 3.4.1 Code
> Pentium, Pentium Pro and Pentium II processors have a cache line size
> of 32 bytes. Since the prefetch buffers fetch on 16-byte boundaries,
> code alignment has a direct impact on prefetch buffer efficiency.
Since the pentium/pmmx has two independent prefetch-buffers, this
doesn't mnatter to these chips as it matters to other chips
in this family.
>
> For optimal performance across the Intel Architecture family, it is
> recommended that:
This is quite true. It does not really matter on the pentium, so
aligning them to 16 is not that bad (except for wasted
memory).
> Well, there is a good reason to not supply the -malign options on current
> versions of egcs: If not given, egcs will now use the above strategy, ie.
> pad code up to a 16-byte boundary if the padding required is 7 bytes or
> less.
Exactly. But there are good reasons to supply a variety of switches with a
variety of compilers....
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---==---(_)__ __ ____ __ Marc Lehmann +--
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The choice of a GNU generation |
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