#The tsc_bug will show for all CPUs made by Centaur/IDT which say they have
#a TSC. It will also show for CPUs made by Cyrix/IBM which say they have
#both a TSC and MMX.
This is just WRONG. PERIOD. *NOT* all Centaur/IDT processors are affected,
only step 0's. And *NOT* all Cyrix/IBM's w/MMX have this problem, only
those prior to step 0, rev 3, excluding that stepping. Otherwise, the TSC
is FINE in BOTH of these processors. NEVER assume something is broken from
such wide variables. It's not The Right Thing(tm). If it's not ALL the
processors, than don't assume it's all. PLEASE. However, otherwise, the
patch looks okay here. Except for above bitch. :)
-Phil R. Jaenke (kernel@nls.net / prj@nls.net)
TheGuyInCharge(tm), Ketyra Designs - We get paid to break stuff :)
Linux pkrea.ketyra.INT 2.0.33 #15 Sat Apr 18 00:40:21 EDT 1998 i586
Linux eiterra.nls.net 2.0.33 #15 Fri Apr 17 00:22:13 EDT 1998 i586
- Linus says for 'brave people only.' I say 'keep a backup.' - :)
-
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