> > > IMHO this is a trade-off. If one wants to have the processor dissipating
> > > < 150mW when Linux is idle, one has to power down the 200MHz or so
> > > 64-bit TSC counter circuitry.
> >
> > The Centaur doesnt have this bug and still has a low power mode. They do
> > it right. So it is a bug in the Cyrix chip.
>
> The Centaur C6, just like the Intel CPUs, enters a low power mode when
> the CPU executes a HALT instruction (i.e. when Linux is idle). However,
> it is not the same low power mode as found in the Cyrix 6x86 CPUs.
>
> Just like the Intel and the AMD K5/K6 chips, the Centaur C6 will still
> dissipate around 2.5 Watts in this low power mode.
>
> OTOH when the clock is _stopped_ (e.g. APM), the Centaur, just like the
> Intel and the AMD K5/K6, will dissipate around 350 mW. However, coming
> out of a clock stop condition is expensive in terms of clock cycles,
> because the CPU internal clock PLL must re-synchronize with the external
> clock input.
Just to add few words on this thread:
Are you sure that stopping and restarting a 200 MHz oscillator
nearly 100 times per second does not consume more power than
staying in idle mode ?
Maybe this feature will be a lot more interresting when the
variable HZ will be configurable at runtime (while not
doing anything, Hz could go down to 10 or less), but for now
I just would like to compare stanby time of battery powered PC.
Just my Euro 0.02,
Etienne.
----------- etienne.lorrain@ibm.net
-- hdc: irq timeout: status=0xd0 { Busy }
-- ide1: reset: success
----------> I like Linux !
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