Re: [Patch v4 09/13] perf/x86/intel: Setup PEBS data configuration and enable legacy groups

[Mi, Dapeng]

On 6/21/2025 5:41 PM, Peter Zijlstra wrote:
> On Fri, Jun 20, 2025 at 10:39:05AM +0000, Dapeng Mi wrote:
>
>> +static inline void __intel_pmu_update_event_ext(int idx, u64 ext)
>> +{
>> +	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
>> +	u32 msr = idx < INTEL_PMC_IDX_FIXED ?
>> +		  x86_pmu_cfg_c_addr(idx, true) :
>> +		  x86_pmu_cfg_c_addr(idx - INTEL_PMC_IDX_FIXED, false);
>> +
>> +	cpuc->cfg_c_val[idx] = ext;
>> +	wrmsrq(msr, ext);
>> +}
>> +static inline unsigned int x86_pmu_cfg_c_addr(int index, bool gp)
>> +{
>> +	u32 base = gp ? MSR_IA32_PMC_V6_GP0_CFG_C : MSR_IA32_PMC_V6_FX0_CFG_C;
>> +
>> +	return base + (x86_pmu.addr_offset ? x86_pmu.addr_offset(index, false) :
>> +					     index * MSR_IA32_PMC_V6_STEP);
>> +}
> This seems like an aweful lot of conditions just to get an ddress.
>
> Also, IIRC we have intel_pmu_v6_addr_offset() and that does: index *
> MSR_IA32_PMC_V6_STEP, so something is very redundant here.

Hmm, the intent of adding this helper is just to follow the existed helpers
like x86_pmu_event_addr(), but considering currently only
__intel_pmu_update_event_ext() need to touch the XXX_CFG_C MSRs, we may not
need to an dedicated helper. Would remove this helper.


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