Re: [net-next PATCH v2 2/2] net: mdio: Add MDIO bus controller for Airoha AN7583

[Andrew Lunn]

On Tue, Jun 17, 2025 at 11:16:53AM +0200, Christian Marangi wrote:
> Airoha AN7583 SoC have 2 dedicated MDIO bus controller in the SCU
> register map. To driver register an MDIO controller based on the DT
> reg property and access the register by accessing the parent syscon.
> 
> The MDIO bus logic is similar to the MT7530 internal MDIO bus but
> deviates of some setting and some HW bug.
> 
> On Airoha AN7583 the MDIO clock is set to 25MHz by default and needs to
> be correctly setup to 2.5MHz to correctly work (by setting the divisor
> to 10x).
> 
> There seems to be Hardware bug where AN7583_MII_RWDATA
> is not wiped in the context of unconnected PHY and the
> previous read value is returned.
> 
> Example: (only one PHY on the BUS at 0x1f)
>  - read at 0x1f report at 0x2 0x7500
>  - read at 0x0 report 0x7500 on every address
> 
> To workaround this, we reset the Mdio BUS at every read
> to have consistent values on read operation.
> 
> Signed-off-by: Christian Marangi <ansuelsmth@xxxxxxxxx>

Reviewed-by: Andrew Lunn <andrew@xxxxxxx>

    Andrew