Re: [PATCH 4/5] arm64: dts: qcom: sm6350: Add GPU nodes

[Konrad Dybcio]

On 17.03.2023 09:56, Luca Weiss wrote:
> On Thu Mar 16, 2023 at 12:16 PM CET, Konrad Dybcio wrote:
>> From: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxx>
>>
>> Add Adreno, GPU SMMU and GMU nodes to hook up everything that
>> the A619 needs to function properly.
>>
>> Co-developed-by: Luca Weiss <luca.weiss@xxxxxxxxxxxxx>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxx>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
>> ---
[...]

> What about adding interconnect already? I also have opp-peak-kBps
> additions in the opp table for that. I'll attach the diff I have at the
> end of the email.
I believe the GMU takes care of it internally (or at least should)
with the bandwidth tables we send in a6xx_hfi.c : a6xx_hfi_send_bw_table()


[...]

>>  
>> +		adreno_smmu: iommu@3d40000 {
> 
> This and gmu should be above gpucc @3d90000?
Absolutely.

Konrad
> 
>> +			compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
>> +			reg = <0 0x03d40000 0 0x10000>;
>> +			#iommu-cells = <1>;
>> +			#global-interrupts = <2>;
>> +			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> +			clocks = <&gpucc GPU_CC_AHB_CLK>,
>> +				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
>> +				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
>> +			clock-names = "ahb",
>> +				      "bus",
>> +				      "iface";
>> +
>> +			power-domains = <&gpucc GPU_CX_GDSC>;
>> +		};
>> +
>> +		gmu: gmu@3d6a000 {
>> +			compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu";
>> +			reg = <0 0x03d6a000 0 0x31000>,
>> +			      <0 0x0b290000 0 0x10000>,
>> +			      <0 0x0b490000 0 0x10000>;
>> +			reg-names = "gmu",
>> +				    "gmu_pdc",
>> +				    "gmu_pdc_seq";
>> +
>> +			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
>> +			interrupt-names = "hfi",
>> +					  "gmu";
>> +
>> +			clocks = <&gpucc GPU_CC_AHB_CLK>,
>> +				 <&gpucc GPU_CC_CX_GMU_CLK>,
>> +				 <&gpucc GPU_CC_CXO_CLK>,
>> +				 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
>> +				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
>> +			clock-names = "ahb",
>> +				      "gmu",
>> +				      "cxo",
>> +				      "axi",
>> +				      "memnoc";
>> +
>> +			power-domains = <&gpucc GPU_CX_GDSC>,
>> +					<&gpucc GPU_GX_GDSC>;
>> +			power-domain-names = "cx",
>> +					     "gx";
>> +
>> +			iommus = <&adreno_smmu 5>;
>> +
>> +			operating-points-v2 = <&gmu_opp_table>;
>> +
>> +			status = "disabled";
>> +
>> +			gmu_opp_table: opp-table {
>> +				compatible = "operating-points-v2";
>> +
>> +				opp-200000000 {
>> +					opp-hz = /bits/ 64 <200000000>;
>> +					opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
>> +				};
>> +			};
>> +		};
>> +
>>  		mpss: remoteproc@4080000 {
>>  			compatible = "qcom,sm6350-mpss-pas";
>>  			reg = <0x0 0x04080000 0x0 0x4040>;
>>
>> -- 
>> 2.39.2
> 
> Here's the diff I have for interconnect on top of this:
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> index 4954cbc2c0fc..51c5ac679a32 100644
> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> @@ -1142,6 +1142,8 @@ gpu: gpu@3d00000 {
>  			iommus = <&adreno_smmu 0>;
>  			operating-points-v2 = <&gpu_opp_table>;
>  			qcom,gmu = <&gmu>;
> +			interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &clk_virt SLAVE_EBI_CH0 0>;
> +			interconnect-names = "gfx-mem";
>  			nvmem-cells = <&gpu_speed_bin>;
>  			nvmem-cell-names = "speed_bin";
>  
> @@ -1157,42 +1159,49 @@ gpu_opp_table: opp-table {
>  				opp-850000000 {
>  					opp-hz = /bits/ 64 <850000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
> +					opp-peak-kBps = <8371200>;
>  					opp-supported-hw = <0x02>;
>  				};
>  
>  				opp-800000000 {
>  					opp-hz = /bits/ 64 <800000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> +					opp-peak-kBps = <8371200>;
>  					opp-supported-hw = <0x04>;
>  				};
>  
>  				opp-650000000 {
>  					opp-hz = /bits/ 64 <650000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> +					opp-peak-kBps = <6220000>;
>  					opp-supported-hw = <0x08>;
>  				};
>  
>  				opp-565000000 {
>  					opp-hz = /bits/ 64 <565000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> +					opp-peak-kBps = <5412000>;
>  					opp-supported-hw = <0x10>;
>  				};
>  
>  				opp-430000000 {
>  					opp-hz = /bits/ 64 <430000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> +					opp-peak-kBps = <4068000>;
>  					opp-supported-hw = <0xff>;
>  				};
>  
>  				opp-355000000 {
>  					opp-hz = /bits/ 64 <355000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> +					opp-peak-kBps = <3072000>;
>  					opp-supported-hw = <0xff>;
>  				};
>  
>  				opp-253000000 {
>  					opp-hz = /bits/ 64 <253000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> +					opp-peak-kBps = <2188000>;
>  					opp-supported-hw = <0xff>;
>  				};
>  			};
>