[PATCH net-next v3 44/47] arm64: dts: ls1046a: Add serdes bindings

[Sean Anderson]

This adds bindings for the SerDes devices. They are disabled by default
to prevent any breakage on existing boards.

Signed-off-by: Sean Anderson <sean.anderson@xxxxxxxx>
---

Changes in v3:
- Describe modes in device tree

Changes in v2:
- Use one phy cell for SerDes1, since no lanes can be grouped
- Disable SerDes by default to prevent breaking boards inadvertently.

 .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 179 ++++++++++++++++++
 1 file changed, 179 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 0085e83adf65..0b3765cad383 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -413,6 +413,185 @@ bportals: bman-portals@508000000 {
 			ranges = <0x0 0x5 0x08000000 0x8000000>;
 		};
 
+		/*
+		 * XXX: For SerDes1, lane A uses pins SD1_RX3_P/N! That is, the
+		 * lane numbers and pin numbers are _reversed_. In addition,
+		 * the PCCR documentation is _inconsistent_ in its usage of
+		 * these terms!
+		 *
+		 * PCCR "Lane 0" refers to...
+		 * ==== =====================
+		 *    0 Lane A
+		 *    2 Lane A
+		 *    8 Lane A
+		 *    9 Lane A
+		 *    B Lane D!
+		 */
+		serdes1: phy@1ea0000 {
+			#clock-cells = <1>;
+			#phy-cells = <1>;
+			compatible = "fsl,ls1046a-serdes", "fsl,lynx-10g";
+			reg = <0x0 0x1ea0000 0x0 0x2000>;
+			status = "disabled";
+
+			pccr-0 {
+				fsl,pccr = <0x0>;
+
+				/* PCIe.1 x1 */
+				pcie-0 {
+					fsl,index = <0>;
+					fsl,cfg = <0x1>;
+					fsl,first-lane = <1>;
+					fsl,proto = "pcie";
+				};
+			};
+
+			pccr-8 {
+				fsl,pccr = <0x8>;
+
+				/* SGMII.6 */
+				sgmii-0 {
+					fsl,index = <0>;
+					fsl,cfg = <0x1>;
+					fsl,first-lane = <0>;
+					fsl,proto = "sgmii";
+				};
+
+				/* SGMII.5 */
+				sgmii-1 {
+					fsl,index = <1>;
+					fsl,cfg = <0x1>;
+					fsl,first-lane = <1>;
+					fsl,proto = "sgmii25";
+				};
+
+				/* SGMII.10 */
+				sgmii-2 {
+					fsl,index = <2>;
+					fsl,cfg = <0x1>;
+					fsl,first-lane = <2>;
+					fsl,proto = "sgmii25";
+				};
+
+				/* SGMII.9 */
+				sgmii-3 {
+					fsl,index = <3>;
+					fsl,cfg = <0x1>;
+					fsl,first-lane = <3>;
+					fsl,proto = "sgmii25";
+				};
+			};
+
+			pccr-9 {
+				fsl,pccr = <0x9>;
+
+				/* QSGMII.6,5,10,1 */
+				qsgmii-1 {
+					fsl,index = <1>;
+					fsl,cfg = <0x1>;
+					fsl,first-lane = <1>;
+					fsl,proto = "qsgmii";
+				};
+			};
+
+			pccr-b {
+				fsl,pccr = <0xb>;
+
+				/* XFI.10 */
+				xfi-0 {
+					fsl,index = <0>;
+					fsl,cfg = <0x2>;
+					fsl,first-lane = <2>;
+					fsl,proto = "xfi";
+				};
+
+				/* XFI.9 */
+				xfi-1 {
+					fsl,index = <1>;
+					fsl,cfg = <0x1>;
+					fsl,first-lane = <3>;
+					fsl,proto = "xfi";
+				};
+			};
+		};
+
+		serdes2: phy@1eb0000 {
+			#clock-cells = <1>;
+			#phy-cells = <2>;
+			compatible = "fsl,ls1046a-serdes", "fsl,lynx-10g";
+			reg = <0x0 0x1eb0000 0x0 0x2000>;
+			status = "disabled";
+
+			pccr-0 {
+				fsl,pccr = <0>;
+
+				pcie-0 {
+					fsl,index = <0>;
+					fsl,proto = "pcie";
+
+					/* PCIe.1 x1 */
+					cfg-1 {
+						fsl,cfg = <0x1>;
+						fsl,first-lane = <1>;
+					};
+
+					/* PCIe.1 x4 */
+					cfg-3 {
+						fsl,cfg = <0x3>;
+						fsl,first-lane = <0>;
+						fsl,last-lane = <3>;
+					};
+				};
+
+				pcie-2 {
+					fsl,index = <2>;
+					fsl,proto = "pcie";
+
+					/* PCIe.2 x1 */
+					cfg-1 {
+						fsl,cfg = <0x1>;
+						fsl,first-lane = <2>;
+					};
+
+					/* PCIe.3 x2 */
+					cfg-2 {
+						fsl,cfg = <0x2>;
+						fsl,first-lane = <2>;
+						fsl,last-lane = <3>;
+					};
+
+					/* PCIe.3 x1 */
+					cfg-3 {
+						fsl,cfg = <0x3>;
+						fsl,first-lane = <3>;
+					};
+				};
+			};
+
+			pccr-2 {
+				fsl,pccr = <0x2>;
+
+				sata-0 {
+					fsl,index = <0>;
+					fsl,cfg = <0x1>;
+					fsl,first-lane = <3>;
+					fsl,proto = "sata";
+				};
+			};
+
+			pccr-8 {
+				fsl,pccr = <0x8>;
+
+				/* SGMII.2 */
+				sgmii-1 {
+					fsl,index = <1>;
+					fsl,cfg = <0x1>;
+					fsl,first-lane = <1>;
+					fsl,proto = "sgmii";
+				};
+			};
+		};
+
 		dcfg: dcfg@1ee0000 {
 			compatible = "fsl,ls1046a-dcfg", "syscon";
 			reg = <0x0 0x1ee0000 0x0 0x1000>;
-- 
2.35.1.1320.gc452695387.dirty