Re: [PATCH] arm64: dts: ls1028a: add interrupt to Root Complex Event Collector

[Michael Walle]

Am 2021-03-04 12:37, schrieb Shawn Guo:
> On Tue, Feb 09, 2021 at 01:52:59AM +0100, Michael Walle wrote:
> > The legacy interrupt INT_A is hardwired to the event collector. RCEC 
> > is
> > bascially supported starting with v5.11. Having a correct interrupt, 
> > will
> > make RCEC at least probe correctly.
> >
> > There are still issues with how RCEC is implemented in the RCiEP on 
> > the
> > LS1028A. RCEC will report an error, but it cannot find the correct
> > subdevice.
> >
> > Signed-off-by: Michael Walle <michael@xxxxxxxx>
> > ---
> >  arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 6 ++++++
> >  1 file changed, 6 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi 
> > b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > index 262fbad8f0ec..c1f2f402ad53 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > @@ -1114,6 +1114,12 @@
> >  					full-duplex;
> >  				};
> >  			};
> > +
> > +			rcec@1f,0 {
>
> Just curious how unit-address comes to '1f,0'?

You mean that it's pci dev 1f func 0?
0x00f800 >> 11 == 0x1f

See also:
https://elixir.bootlin.com/linux/v5.12-rc1/source/scripts/dtc/checks.c#L916

-michael

> Shawn
>
> > +				reg = <0x00f800 0 0 0 0>;
> > +				/* IEP INT_A */
> > +				interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> > +			};
> >  		};
> >
> >  		rcpm: power-controller@1e34040 {
> > --
> > 2.20.1