Re: perf events ring buffer memory barrier on powerpc

From: Frederic Weisbecker
Date: Mon Oct 28 2013 - 06:02:09 EST

2013/10/25 Peter Zijlstra <peterz@xxxxxxxxxxxxx>:
> On Wed, Oct 23, 2013 at 03:19:51PM +0100, Frederic Weisbecker wrote:
> I would argue for:
> READ ->data_tail READ ->data_head
> smp_rmb() (A) smp_rmb() (C)
> WRITE $data READ $data
> smp_wmb() (B) smp_mb() (D)
> STORE ->data_head WRITE ->data_tail
> Where A pairs with D, and B pairs with C.
> I don't think A needs to be a full barrier because we won't in fact
> write data until we see the store from userspace. So we simply don't
> issue the data WRITE until we observe it.
> OTOH, D needs to be a full barrier since it separates the data READ from
> the tail WRITE.
> For B a WMB is sufficient since it separates two WRITEs, and for C an
> RMB is sufficient since it separates two READs.

Hmm, I need to defer on you for that, I'm not yet comfortable with
picking specific barrier flavours when both write and read are
involved in a same side :)
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