Re: perf events ring buffer memory barrier on powerpc
From: Peter Zijlstra
Date: Mon Oct 28 2013 - 05:23:28 EST
On Sun, Oct 27, 2013 at 11:00:33AM +0200, Victor Kaplansky wrote:
> Peter Zijlstra <peterz@xxxxxxxxxxxxx> wrote on 10/25/2013 07:37:49 PM:
> > I would argue for:
> > READ ->data_tail READ ->data_head
> > smp_rmb() (A) smp_rmb() (C)
> > WRITE $data READ $data
> > smp_wmb() (B) smp_mb() (D)
> > STORE ->data_head WRITE ->data_tail
> > Where A pairs with D, and B pairs with C.
> 1. I agree. My only concern is that architectures which do use atomic
> with memory barriers, will issue two consecutive barriers now, which is
Yeah, although that would be fairly easy to optimize by the CPUs itself;
not sure they actually do this though.
But we don't really have much choice aside of introducing things like:
smp_wmb__after_local_$op; and I'm fairly sure people won't like adding a
ton of conditional barriers like that either.
> 2. I think the comment in "include/linux/perf_event.h" describing
> "data_head" and
> "data_tail" for user space need an update as well. Current version -
Oh, indeed. Thanks; I'll update that too!
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