Re: [PATCH 3/3] clk: tegra: T114: add DFLL DVCO reset control

From: Paul Walmsley
Date: Tue Jun 11 2013 - 05:47:22 EST

On Tue, 11 Jun 2013, Prashant Gaikwad wrote:

> Why not implement these APIs in DFLL clock driver itself and pass RST address
> register to driver?

The DFLL DVCO reset registers are CAR registers, not DFLL registers.
Functions that operate on registers in one IP block shouldn't be located
in another IP block's driver.

- Paul
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