Re: [PATCHv2 3/3] ARM: Work around faulty ISAR0 register in someKrait CPUs

From: Stephen Boyd
Date: Mon Mar 18 2013 - 14:46:33 EST

On 03/18/13 11:34, Will Deacon wrote:
> On Mon, Mar 18, 2013 at 06:28:57PM +0000, Stephen Boyd wrote:
>> From: Stepan Moskovchenko <stepanm@xxxxxxxxxxxxxx>
>> Some early versions of the Krait CPU design incorrectly indicate
>> that they only support the UDIV and SDIV instructions in Thumb
>> mode when they actually support them in ARM and Thumb mode. It
>> seems that these CPUs follow the DDI0406B ARM ARM which has two
>> possible values for the divide instructions field, instead of the
>> DDI0406C document which has three possible values.
>> Work around this problem by checking the MIDR against Krait CPUs
>> with this faulty ISAR0 register and force the hwcaps to indicate
>> support in both modes.
>> Cc: Will Deacon <will.deacon@xxxxxxx>
>> Signed-off-by: Stepan Moskovchenko <stepanm@xxxxxxxxxxxxxx>
>> [sboyd: Rewrote commit text to reflect real reasoning now that
>> we autodetect udiv/sdiv]
>> Signed-off-by: Stephen Boyd <sboyd@xxxxxxxxxxxxxx>
>> ---
>> arch/arm/mm/proc-v7.S | 15 +++++++++++++++
>> 1 file changed, 15 insertions(+)
> Acked-by: Will Deacon <will.deacon@xxxxxxx>

Thanks. Put all three in the patch tracker.

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