Re: gpio-sch GPIO_SYSFS access
From: Samuel Ortiz
Date: Fri Feb 08 2013 - 06:07:27 EST
On Fri, Feb 08, 2013 at 02:36:16AM -0800, Darren Hart wrote:
> On 02/08/2013 12:49 AM, Samuel Ortiz wrote:
> >> Well, this happens when the driver in question gets removed by another
> >> driver.
> > removed by another driver ? I'm not sure I understand what that means.
> In my case, the gpio-sch probe function runs and creates the gpiochip
> with 14 GPIO lines. Later lpc-sch probe runs,
That's weird: The lpc-sch probe should run first. Then the gpio-sch probe
should be called when lpc-sch adds the MFD cells as platform devices, from
So someone is adding gpio-sch as a platform device, and that is wrong.
> adds devices to the mfd
> device list, fails the WDT base address as described below, and then
> removes the devices in the mfd device list, which triggers the removal
> of the gpio-sch device.
> If I just skip the WDT lookup and not abort, then things work as I had
> expected. Sooo... does it make sense to remove ALL the MFD device when
> the read of the WDTBA registers indicates "Disabled"? Seems extreme to me.
Yes, that's a bit rough. But I think you have a more fundamental problem where
you're probing both LPC and your GPIO driver.
> >> Samuel, does it make sense for CONFIG_GPIO_SCH to require
> >> CONFIG_LPC_SCH? I'm building for a Queensbay (Atom E6xx + EG20T PCH).
> >> There is no SCH as I understand things. Can these be decoupled?
> > They actually don't have code dependency, GPIO_SCH selects LPC_SCH beacause
> > the MFD parts actually creates the GPIO device.
> > So you're saying Queensbay use the same GPIO IP block without actually having
> > SCH ?
> That is how I currently understand it. These drivers appear to have been
> originaly written for the Silverthorne (Z5xx) CPUs and the Intel SCH
If your lpc_sch_probe routine runs, you basically have an LPC on your PCI bus
here. As I said, PCI probes lpc_sch _and_ gpio_sch is probed as well (As a
platform device, probably coming from your SFI tables or so). Probing both is
problematic, especially since you do have an LPC sitting on your PCI bus.
Intel Open Source Technology Centre
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