Re: [PATCH v3 4/7] x86/tlb: add tlb flush all factor for specificCPUs

[H. Peter Anvin]

On 05/08/2012 07:03 AM, Alex Shi wrote:
> --- a/arch/x86/kernel/cpu/intel.c
> +++ b/arch/x86/kernel/cpu/intel.c
> @@ -610,6 +610,35 @@ void intel_tlb_lookup(const unsigned char desc)
>  	}
>  }
>  
> +void intel_tlb_flushall_factor_set(struct cpuinfo_x86 *c)
> +{
> +	switch (c->x86_model) {
> +	case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
> +		tlb_flushall_factor = 0;
> +		break;
> +	case 26: /* 45 nm nehalem, "Bloomfield" */
> +	case 30: /* 45 nm nehalem, "Lynnfield" */
> +	case 37: /* 32 nm nehalem, "Clarkdale" */
> +	case 44: /* 32 nm nehalem, "Gulftown" */
> +	case 46: /* 45 nm nehalem-ex, "Beckton" */
> +		tlb_flushall_factor = 64;
> +		break;
> +	case 42: /* SandyBridge */
> +	case 45: /* SandyBridge, "Romely-EP" */
> +		tlb_flushall_factor = 32;
> +		break;
> +	case 28: /* Atom */
> +	case 47: /* 32 nm Xeon E7 */
> +	case 14: /* 65 nm core solo/duo, "Yonah" */
> +	case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
> +	case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
> +	case 29: /* six-core 45 nm xeon "Dunnington" */
> +
> +	default:
> +		tlb_flushall_factor = 0;
> +	}
> +}
> +

This uses x86_model without qualifying it x86 (family), however that is
meaningless.  All the CPUs you are dealing with above have c->x86 == 6,
but you need to handle others correctly (even if that just means
defaulting it to zero.)

One way to do that is to do:

switch ((c->x86 << 8) + c->x86_model) {

... and use numbers like 0x62d instead of 45.

	-hpa


-- 
H. Peter Anvin, Intel Open Source Technology Center
I work for Intel.  I don't speak on their behalf.

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