Re: [PATCH] NVMe: Fix compilation on architecturs without readq/writeq
From: Hitoshi Mitake
Date: Sat Feb 04 2012 - 10:25:33 EST
On Tue, Jan 31, 2012 at 12:03, Linus Torvalds
> On Sun, Jan 29, 2012 at 12:02 AM, Hitoshi Mitake <h.mitake@xxxxxxxxx> wrote:
>> I don't know about the minor architectures, but some of them,
>> like alpha, seems to do reordering of memory access agressively.
>> Is the reordering is applied to io rw?
>> Should memory barriers be placed between two readl/writel?
> No need to place barriers - the "readl/writel()" functions are ordered
> in themselves. There are non-ordered versions in theory
> ("writel_relaxed()") for things like frame buffers etc that actively
> want the ordering, but that's a separate issue entirely.
> You do want to make sure that they aren't in the same C expression, so
> that the compiler doesn't re-order the expression. IOW, if you just do
> return (readl(addr+4) << 32) | readl(addr);
> then that doesn't have any ordering at all simply because there is
> none at the C level. But
> u64 val;
> val = readl(addr);
> val |= readl(addr+4) << 32;
> is well-defined and must read the low word first - both at the C level
> *and* at the CPU level. Anything else would be a bug in the
> architecture "readl()" implementation or the hardware.
> (On x86, for example, a "readl()" is just a memory access, but while
> x86 can re-order reads to regular memory in hardware, that is *not*
> true of IO memory accesses. On architectures like POWER, 'readl()'
> implies synchronization instructions)
Thanks for your description.
Now I can understand the semantics of readl/writel of the kernel.
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