Re: arm: Optimization for ethernet MAC handling at91_ether.c

From: Eric Dumazet
Date: Tue Jan 12 2010 - 14:24:54 EST

Le 12/01/2010 20:03, James Kosin a écrit :
> Scratch that. The interrupt doesn't queue up or send another packet directly. So, it wouldn't help on performance here. But, may in other implementations that queue/transmit packets in the ISR. At least in the case where the transmitter is limited to one.

It could, at least on SMP. tx completion wakes a blocked sender, while
this cpu continue with RX handling (possibly expensive)

But even on UP, doing tx completion before rx handling allows
a better reuse of skb just freed (and partly present in cpu cache, if available).

Start of IRQ

1) tx completion
-> free a skb

2) rx handling:
-> allocate an skb, kmalloc() reuses previous one, still in cpu cache.

End of IRQ
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at
Please read the FAQ at