Re: [PATCH C 08/13] OMAP3 clock: put DPLL into bypass if bypass rate = clk->rate, not hardware rate

From: Russell King - ARM Linux
Date: Thu Jan 29 2009 - 05:35:28 EST

On Wed, Jan 28, 2009 at 12:08:32PM -0700, Paul Walmsley wrote:
> When a non-CORE DPLL is enabled via omap3_noncore_dpll_enable(), use
> the user's desired rate in clk->rate to determine whether to put the
> DPLL into bypass or lock mode, rather than reading the DPLL's current
> idle state from its hardware registers.
> This fixes a bug observed when leaving retention. Non-CORE DPLLs were
> not being relocked when downstream clocks re-enabled; rather, the DPLL
> entered bypass mode.
> Problem reported by Tero Kristo <tero.kristo@xxxxxxxxx>.
> linux-omap source commit is 8b1f0bd44fe490ec631230c8c040753a2bda8caa.
> Signed-off-by: Paul Walmsley <paul@xxxxxxxxx>
> Signed-off-by: Tony Lindgren <tony@xxxxxxxxxxx>
> Cc: Tero Kristo <tero.kristo@xxxxxxxxx>

Patch 6 did it this way. Patch 7 changed it to use omap2_get_dpll_rate()
and this patch changes it back. What's the point of submitting all this
detail? It's just pure noise. Collapse these three patches into one
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