Re: dma_alloc_coherent() on PPC32: physical addresses above 2G possible?

[Stefan Richter]

Arjan van de Ven wrote:
> On Sun, 20 Jul 2008 21:25:51 +0200
> Stefan Richter <stefanr@xxxxxxxxxxxxxxxxx> wrote:
>> 	if (dev->needs_dma_mask_workaround)
>> 		pci_set_consistent_dma_mask(pdev, DMA_31BIT_MASK);
>> 	allocate_something_special;
>> 	if (dev->needs_dma_mask_workaround)
>> 		pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
...
> something like this.
> But realistically, how many consistent/coherent allocations do you have?
> some ring buffers and other one time stuff surely... but not after that?

It's for DMA programs (i.e. lists of descriptors), not for the data DMA
buffers themselves.  FireWire controllers have several DMA contexts for
isochronous and asynchronous reception and transmission, and some
others.  Only context programs for isochronous reception need the
workaround.

We are dynamically appending new descriptors during runtime.  I.e. the
affected allocations happen during setup of the DMA context and
sometimes while the DMA context is active.  Particularly, in
drivers/firewire/fw-ohci.c:
	ohci_allocate_iso_context
		context_init
			context_add_buffer  <--
and
	ohci_queue_iso
		ohci_queue_iso_receive_dualbuffer
			context_get_descriptors
				context_add_buffer  <--

The other unaffected context types use context_add_buffer too.
-- 
Stefan Richter
-=====-==--- -=== =-=--
http://arcgraph.de/sr/
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