Re: [PATCH 1/2] x86: mtrr cleanup for converting continuous to discrete layout v7

From: Yinghai Lu
Date: Tue Apr 29 2008 - 13:12:50 EST

On Tue, Apr 29, 2008 at 4:51 AM, Gabriel C <nix.or.die@xxxxxxxxxxxxxx> wrote:
>
> Yinghai Lu wrote:
> > On Tue, Apr 29, 2008 at 3:30 AM, Yinghai Lu <yhlu.kernel@xxxxxxxxx> wrote:
> >> On Tue, Apr 29, 2008 at 2:47 AM, Gabriel C <nix.or.die@xxxxxxxxxxxxxx> wrote:
> >> > Yinghai Lu wrote:
> >> > > some BIOS like to use continus MTRR layout, and may X driver can not add
> >> > > WB entries for graphical cards when 4g or more RAM installed.
> >> > >
> >> > > the patch will change MTRR to discrete.
> >> > >
> >> > > mtrr_chunk_size= could be used to have smaller continuous block to hold holes.
> >> > > default is 256m, could be set according to size of graphics card memory.
> >> > >
> >> > > v2: fix -1 for UC checking
> >> > > v3: default to disable, and need use enable_mtrr_cleanup to enable this feature
> >> > > skip the var state change warning.
> >> > > remove next_basek in range_to_mtrr()
> >> > > v4: correct warning mask.
> >> > > v5: CONFIG_MTRR_SANITIZER
> >> > > v6: fix 1g, 2g, 512 aligment with extra hole
> >> > > v7: gran_sizek to prevent running out of MTRRs.
> >> > >
> >> >
> >> > With this version ( and patch http://lkml.org/lkml/2008/4/29/97 ) applyed on latest linus git tree
> >> > the box OOPS'es early.
> >> >
> >> > Sorry I don't have time right now to write down the part of the OOPS I can see on monitor , I can try to find
> >> > some time later.
> >> >
> >> > In any way OOPS'es on __free_one_page+0x191/0x21e
> >>
> >> thanks. found one problem with hole_basek ...
> >>
> >> will send you v8, and hope it will be last version.
> >
> > please try v8, it should get rid of the 8m entry. it need patch
> > http://lkml.org/lkml/2008/4/29/97 too.
>
> Box does boot with v8 but now I get that warning you fixed in v2 again =):
>
> ....
> [ 0.000000] Linux version 2.6.25-06058-ga01e035-dirty (crazy@thor) (gcc version 4.3.0 (Frugalware Linux) ) #805 SMP PREEMPT Tue Apr 29 13:04:49 CEST 2008
> [ 0.000000] Command line: root=/dev/sdb1 ro debug vga=0x317
> [ 0.000000] BIOS-provided physical RAM map:
> [ 0.000000] BIOS-e820: 0000000000000000 - 000000000009cc00 (usable)
> [ 0.000000] BIOS-e820: 000000000009cc00 - 00000000000a0000 (reserved)
> [ 0.000000] BIOS-e820: 00000000000e4000 - 0000000000100000 (reserved)
> [ 0.000000] BIOS-e820: 0000000000100000 - 00000000cf550000 (usable)
> [ 0.000000] BIOS-e820: 00000000cf550000 - 00000000cf55e000 (ACPI data)
> [ 0.000000] BIOS-e820: 00000000cf55e000 - 00000000cf5e0000 (ACPI NVS)
> [ 0.000000] BIOS-e820: 00000000cf5e0000 - 00000000cf600000 (reserved)
> [ 0.000000] BIOS-e820: 00000000fee00000 - 00000000fee01000 (reserved)
> [ 0.000000] BIOS-e820: 00000000ffc00000 - 0000000100000000 (reserved)
> [ 0.000000] BIOS-e820: 0000000100000000 - 000000012c000000 (usable)
> [ 0.000000] Entering add_active_range(0, 0, 156) 0 entries of 256 used
> [ 0.000000] Entering add_active_range(0, 256, 849232) 1 entries of 256 used
> [ 0.000000] Entering add_active_range(0, 1048576, 1228800) 2 entries of 256 used
> [ 0.000000] max_pfn_mapped = 1228800
> [ 0.000000] x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106
> [ 0.000000] After WB checking
> [ 0.000000] MTRR MAP PFN: 0000000000000000 - 000000000012c000
> [ 0.000000] After UC checking
> [ 0.000000] MTRR MAP PFN: 0000000000000000 - 00000000000cf600
> [ 0.000000] MTRR MAP PFN: 0000000000100000 - 000000000012c000
> [ 0.000000] MTRR MAP PFN: 00000000000cf800 - 00000000000d0000
> [ 0.000000] After sorting
> [ 0.000000] MTRR MAP PFN: 0000000000000000 - 00000000000cf600
> [ 0.000000] MTRR MAP PFN: 00000000000cf800 - 00000000000d0000
> [ 0.000000] MTRR MAP PFN: 0000000000100000 - 000000000012c000
> [ 0.000000] range0: 0000000000000000 - 00000000c0000000
> [ 0.000000] Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB
> [ 0.000000] Setting variable MTRR 1, base: 2048MB, range: 1024MB, type WB
> [ 0.000000] range: 00000000c0000000 - 00000000d0000000
> [ 0.000000] Setting variable MTRR 2, base: 3072MB, range: 256MB, type WB
> [ 0.000000] hole: 00000000cc000000 - 00000000d0000000
> [ 0.000000] Setting variable MTRR 3, base: 3264MB, range: 64MB, type UC
> [ 0.000000] rangeX: 00000000d0000000 - 00000000d0000000
> [ 0.000000] range0: 0000000100000000 - 0000000120000000
> [ 0.000000] Setting variable MTRR 4, base: 4096MB, range: 512MB, type WB
> [ 0.000000] range: 0000000120000000 - 0000000130000000
> [ 0.000000] Setting variable MTRR 5, base: 4608MB, range: 256MB, type WB
> [ 0.000000] hole: 000000012c000000 - 0000000130000000
> [ 0.000000] Setting variable MTRR 6, base: 4800MB, range: 64MB, type UC
> [ 0.000000] DONE variable MTRRs
> [ 0.000000] x86 PAT enabled: cpu 0, old 0x7010600070106, new 0x7010600070106
> [ 0.000000] After WB checking
> [ 0.000000] MTRR MAP PFN: 0000000000000000 - 00000000000d0000
> [ 0.000000] MTRR MAP PFN: 0000000000100000 - 0000000000130000
> [ 0.000000] After UC checking
> [ 0.000000] MTRR MAP PFN: 0000000000000000 - 00000000000cc000
> [ 0.000000] MTRR MAP PFN: 0000000000100000 - 000000000012c000
> [ 0.000000] After sorting
> [ 0.000000] MTRR MAP PFN: 0000000000000000 - 00000000000cc000
> [ 0.000000] MTRR MAP PFN: 0000000000100000 - 000000000012c000
> [ 0.000000] WARNING: BIOS bug: CPU MTRRs don't cover all of memory, losing 757MB of RAM.

so
> [ 0.000000] MTRR MAP PFN: 0000000000000000 - 00000000000cf600
> [ 0.000000] MTRR MAP PFN: 00000000000cf800 - 00000000000d0000
> [ 0.000000] MTRR MAP PFN: 0000000000100000 - 000000000012c000
===>
> [ 0.000000] MTRR MAP PFN: 0000000000000000 - 00000000000cc000
> [ 0.000000] MTRR MAP PFN: 0000000000100000 - 000000000012c000

please try
mtrr_chunk_size=512m mtrr_gran_size=128m
or
mtrr_chunk_size=256m mtrr_gran_size=128m

YH
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