Re: Breakage caused by unreviewed patch in x86 tree

[Arjan van de Ven]

On Sun, 27 Apr 2008 19:03:59 -0400
James Bottomley <James.Bottomley@xxxxxxxxxxxxxxxxxxxxx> wrote:

> On Sun, 2008-04-27 at 15:58 -0700, Arjan van de Ven wrote:
> > On Sun, 27 Apr 2008 16:51:25 -0400
> > James Bottomley <James.Bottomley@xxxxxxxxxxxxxxxxxxxxx> wrote:
> > When you're mapping device memory, uncached is the safe default. 
> 
> Well, for certain device mailboxes, uncached does mean less
> performant. The voyager breakage was exceptional ... I expect other
> problems just to result in a loss of performance that caching gave by
> improving the bursting.  If we're lucky, the PCI bridge cache might
> hide a lot of this.

on a PC, NONE of the ioremap()s of PCI stuff were cached before, with the
exception of prefetchable ranges, that some bioses set up a write-combining MTRR for.
(and write-combining is effectively "uncached but with write buffering")

If you look at at what kind of devices have prefetchable ranges, you get two answers:
1) video cards
2) some IB adapters


So your argument that this might change PCI stuff is just false.

Your argument that this "99.9%->100% uncached" should have been announced/discussed
in public, sure. But to make this big a deal out of it?

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