LFENCE instruction (was: [rfc][patch 3/3] x86: optimise barriers)

[Mikulas Patocka]

> According to latest memory ordering specification documents from Intel 
> and AMD, both manufacturers are committed to in-order loads from 
> cacheable memory for the x86 architecture. Hence, smp_rmb() may be a 
> simple barrier.
>
> http://developer.intel.com/products/processor/manuals/318147.pdf 
> http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24593.pdf

Hi

I'm just wondering about one thing --- what is LFENCE instruction good 
for?

SFENCE is for enforcing ordering in write-combining buffers (it doesn't 
have sense in write-back cache mode).
MFENCE is for preventing of moving stores past loads.

But what is LFENCE for? I read the above documents and they already say 
that CPUs have ordered loads.

In Intel instruction reference, the description for LFENCE is copied from 
SFENCE (with the word "store" replaced with the word "load"), so it 
doesn't really give much insight into the operation of the instruction.

Or is LFENCE just a no-op reserved for the possibility that Intel would 
relax ordering rules?

Mikulas
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