Re: PCI-Express root complex quirk in virtual P2P bridge

From: David Miller
Date: Wed Jun 13 2007 - 02:40:10 EST

From: Kumar Gala <galak@xxxxxxxxxxxxxxxxxxx>
Date: Wed, 13 Jun 2007 01:26:33 -0500

> I was hoping to get some guidance on how to handle a quirk in how the
> virtual P2P bridge works on some embedded PowerPC PCI-Express root
> complex controllers. In the controllers I'm dealing with when we
> change PCI_PRIMARY_BUS in pci_scan_bridge the ability to send config
> cycles to the controller itself becomes effected. The controller
> only sends config cycles internally if the bus # in the config cycle
> matches the PCI_PRIMARY_BUS. We end up going from being 0 to 3 in
> the particular setup and at the point we set PCI_PRIMARY_BUS to 3 we
> are no longer able to send internal config cycles.
> What we need is that either a quirk or pcibios code needs to get call
> right after we set PCI_PRIMARY_BUS so we can fixup the bus number
> relationship. I was wondering if anyone had suggestions on how best
> to handle this.

I would suggest building the PCI device tree using the OF device tree.
64-bit PowerPC does this already, perhaps you can use some of the
existing code for your case too.

Sparc64 does as 64-bit PowerPC does.

I can't even program the PCI-E root controller in PCI config space on
sparc64 Niagara systems, so I just virtualize it.
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