Re: Uses for memory barriers

[Segher Boessenkool]

> > In both cases, the CPU might "discard" the write, if there are no  
> > intervening
> > reads or writes to the same location.  The only difference between  
> > your
>
> How can it know that?

Because it holds the cache line in the "O" (owned) state, for example.

And it doesn't matter how a CPU would do this; the only thing that
matters is that you do not assume anything that is not guaranteed
by the model.


Segher

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