Re: Uses for memory barriers

[Paul E. McKenney]

On Tue, Sep 12, 2006 at 10:01:43AM +0100, David Howells wrote:
> Paul E. McKenney <paulmck@xxxxxxxxxx> wrote:
> 
> > 2.	All stores to a given single memory location will be perceived
> > 	as having occurred in the same order by all CPUs.
> 
> Does that take into account a CPU combining or discarding coincident memory
> operations?

I believe so.

> For instance, a CPU asked to issue two writes to the same location may discard
> the first if it hasn't done it yet.

If I understand your example correctly, in that case, all CPUs would agree
that the given CPU's stores happened consecutively.  Yes, they might not
see the intermediate value, but their view of the sequence of values
would be consistent with the given CPU's pair of stores having happened
at a specific place in the sequence of values.

This is not peculiar to this situation -- consider the following:

	CPU 0		CPU 1		CPU 2		CPU 3

	A=1
			Q1=A				Q3=A
					A=2
							A=3
			Q2=A				Q4=A

None of the CPUs saw CPU 2's first assignment A=2, but all of their
reads are consistent with the 1,2,3 sequence of values.  Your example
(if I understand it correctly) is simply a special case where the
pair of assignments happened on a single CPU.

							Thanx, Paul
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