Re: REGRESSION: the new i386 timer code fails to sync CPUs

[Siddha, Suresh B]

On Sun, Jul 30, 2006 at 11:55:09PM +0200, Matthias Urlichs wrote:
> Hi,
> 
> Arjan van de Ven:
> > if the hardware side is different *speed*.. then a tsc sync ain't going
> > to work... sure we write to it but it's immediately out of sync again
> > 
> No, it's in fact the same speed -- the BIOS just reads it wrongly.

It sounds to me as a BIOS issue. From the boot log, it is quite clear that
TSCs are running at different speeds(different bogomips show this).
This CPU stepping has constant TSC behavior. So this is most probably happening
because of bios setting different core to bus clock ratios for each package.
Different CPU speed BIOS issue that you mention also points to this.

Can you check if your BIOS settings are set to max ratio(15?) available?
or try an updated BIOS?

> 
> I checked: the two date values do advance at the same rate.

Perhaps data overflow(because of unsync TSC's) in timer code calculations
may be causing this?

thanks,
suresh
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