Re: [PATCH] x86/PAE: Fix pte_clear for the >4GB RAM case

[Nick Piggin]

Andi Kleen wrote:

> No it was me who was confused sorry. Somehow i thought it was defined
> away for !SMP
>
> (which would make sense because why would you want a compile barrier
> for a barrier that is only needed on SMP?) 

It is maybe not clearly named. smp_wmb() is a memory barrier to the
regular (eg. RAM) cache coherency domain AFAICT. wmb() is also a
barrier to io memory.

There is nothing to distinguish SMP and UP. I guess sometimes smp_
barriers would not even have to be a barrier() on UP, but other
times they would have to be (eg. in the case of concurrent
interrupts, context switches).

--
SUSE Labs, Novell Inc.
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