Re: [PATCH] cacheline align pagevec structure

[Andrew Morton]

Marcelo Tosatti <marcelo.tosatti@xxxxxxxxxxxx> wrote:
>
> I do not see a problem with changing pagevec to "15" page pointers either, 
> Andrew, is there a special reason for that "16"? Is intentional to align
> to 64 kbytes (IO device alignment)? I dont think that matters much because
> of the elevator which sorts and merges requests anyway?

No, it was just a randomly-chosen batching factor.

The tradeoff here is between

a) lock acquisition frequency versus lock hold time (increasing the size
   helps).

b) icache misses versus dcache misses. (increasing the size probably hurts).

I suspect that some benefit would be seen from making the size very small
(say, 4). And on some machines, making it larger might help.
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