Re: IO-APIC on nforce2 [PATCH]

[Len Brown]

On Wed, 2004-04-14 at 06:37, Maciej W. Rozycki wrote:
> On Wed, 14 Apr 2004, Ross Dickson wrote:

> > The clock skew is an interesting one, I think the clock uses tsc if available
> > to interpolate between timer ints and if so should it not also be used to 
> > validate the timer ints in case of noise? Apparently the clock speeds up not
> > slows down in those cases?
> 
>  With real hardware perhaps it can be debugged.  The interaction between
> the 8254, the 8259As and the APICs seems interesting in the chipset.

> Perhaps the override to INTIN2 is to tell the timer is really unavailable
> directly?

That would be way too subtle for a BIOS writer;-)

> I can't see a way to have an ACPI override that specifies an
> ISA interrupt is not connected to the I/O APIC (unlike with the MPS).

I agree.  And I think the existence of this /proc/interrupts
entry on an ACPI-enabled system should probably go away.

           CPU0       CPU1
  2:          0          0          XT-PIC  cascade

ACPI also doesn't support sharing more than 1 pin on an IRQ.
So if you see a construct like this below, it is also a bug:

IRQ to pin mappings:
IRQ23 -> 0:23-> 0:7

cheers,
-Len


-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/