Re: IO-APIC on nforce2 [PATCH]

[Maciej W. Rozycki]

On Wed, 14 Apr 2004, Ross Dickson wrote:

> e.g. for 2.4.26-rc2 io_apic.c line 1613 or 2.6.5 line 2180 
> 	if (pin1 != -1) {
> 		/*
> 		 * Ok, does IRQ0 through the IOAPIC work?
> 		 */
> +		if(acpi_skip_timer_override)
> +			timer_ack=0;
> 		unmask_IO_APIC_irq(0);
> 
> I might also grab the pci quirk source from the old nforce2 disconnect bit
> patch and try it as a means of detection for automatic trigger. i.e. instead
> of writing the pci config bit, set acpi_skip_timer_override instead - but then
> if someone gets clock skew we would need the kern arg to turn it off - 
> unless the potential for clock skew is fixed.

 Well, the question is whether the timer->INTIN0 routing is hardwired
inside the nforce2 chipset or is it external and thus board-dependent.  
Any way to get this clarified by the chipset's manufacturer?

> The clock skew is an interesting one, I think the clock uses tsc if available
> to interpolate between timer ints and if so should it not also be used to 
> validate the timer ints in case of noise? Apparently the clock speeds up not
> slows down in those cases?

 With real hardware perhaps it can be debugged.  The interaction between
the 8254, the 8259As and the APICs seems interesting in the chipset.  
Perhaps the override to INTIN2 is to tell the timer is really unavailable
directly?  I can't see a way to have an ACPI override that specifies an
ISA interrupt is not connected to the I/O APIC (unlike with the MPS).

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@xxxxxxxxxxxxx, PGP key available        +
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