Re: problem with cache flush routine for G5?

[Benjamin Herrenschmidt]

On Fri, 2004-03-05 at 08:06, Chris Friesen wrote:
> We're running into issues with the "flush_data_cache" routine on the G5.
> 
> For the G5, the L1 dcache is 32K and the L2 cache is 512K. At 128 
> bytes/cacheline, that's 256 and 4096 cachelines, respectively.
> 
> In the existing tree, NUM_CACHE_LINES is set to 128*8, or 1024.  Is this 
> an oversight or am I missing something?
> 
> Also, I'm curious why the dcbf instruction is not used for this.

First of all, why do you need to flush the cache at all ?

If you are talking about the cache flush in the 32 bits bootloaders,
then yes, this seem to be broken, you should ask Tom Rini who
maintain these things.

The kernel proper definitely doesn't contain such a routine.

Ben.


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