Re: x86, ARM, PARISC, PPC, MIPS and Sparc folks please run this

[Alan Cox]

On Sul, 2003-09-07 at 14:53, Jamie Lokier wrote:
> Pavel Machek wrote:
> > Perhaps weak ordering matters when you are writting to the MMIO, too?
> 
> Perhaps, but the code in arch/i386/kernel/cpu/centaur.c seems to try
> hard to set weak ordering for RAM, not the whole address space.

There are three cases I know of where you get weak store ordering that
is visible in some way

#1 Pentium Pro due to an errata, hence the need for lock in the
spin_unlock

#2 Centaur Winchip (where OOSTORE off is worth 10-30% performance on
common tasks). A lot of that has to do with the nature of the CPU and 
the old socket 7 bus stuff. Its not SMP but we have to care about it
for mmio not because mmio is itself out of order (we leave it in order)
but because of DMA. We must ensure that our writes to ram finish
-before- we kick off the hardware copying the data...

#3 Weak store ordering via sse type instructions, where its intentional
and an sfence is needed eventually

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