Re: x86, ARM, PARISC, PPC, MIPS and Sparc folks please run this

[Pavel Machek]

Hi!

> > > x86 gives you coherency and store ordering (barring errata and special
> > > CPU modes)
> > 
> > Special CPU modes? You mean some special SSE stores?
> 
> Take a look at arch/i386/kernel/cpu/centaur.c, and CONFIG_X86_OOSTORE.
> 
> You can change the memory settings to weakly ordered writes, which
> means that a plain write isn't suitable for spin_unlock.  Presumably
> this mode is faster (though I don't see why, if Intel, AMD et al. can
> manage good memory performance without weak writes).

Wow, seems interesting, how much performance does it buy? [Maybe AMD
and Intel just threw a lot of silicon at the problem and it went
away. Centaur solution might be nicer, through -- spin_unlock is so
uncommon that this seems like nice optimalization.]

-- 
Horseback riding is like software...
...vgf orggre jura vgf serr.
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