Re: x86, ARM, PARISC, PPC, MIPS and Sparc folks please run this

[Geert Uytterhoeven]

On Wed, 3 Sep 2003, Jamie Lokier wrote:
> Geert Uytterhoeven wrote:
> > So the store buffer is coherent on 68020 with external MMU, while it
> > isn't on 68040 with internal MMU...
> 
> Does the 68020 even _have_ the equivalent of a store buffer?

Good question :-)

After I sent the previous mail, I realized the '030 has 256 bytes I cache and
256 bytes D cache, while the '020 has 256 bytes I cache only.

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

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